00 / note

Computer engineering work across RTL, embedded systems, packet tools, and testable automation.

01 / degree
focus
computer engineering
base
fayetteville, ar
year
2026
02 / built
capstoneproject clinical balance platform senior build Various verilogmicrocontroller modular Verilog CPU course-born Verilog trafficsimulator Arty A7 / MicroBlaze traffic sim board-level sim · embedded constraints C PCAPSteganography IPv4 LSB steganography packet fields doing odd things C networksnifferproject live packet analytics watch the wire Python MiniFirewall customizable firewall rules small rules C++ portfoliooptimization backtesting + metrics numbers Python stockbacktestertool synthetic stock backtester toy market Python synthproject sine-wave synthesizer signal sketch Python LaserTagProject networked game backend networking practice Java
03 / scraps
iotsecuritydash

security dashboard sketch

messy cloudtaskmanager

FastAPI + JWT task app

useful skeleton promptsandbox

prompt testing bench

token-saver mode pe-dashboard

fund analytics prototype

detour
04 / signals
hardware

RTL design · FPGA systems · embedded integration

security

packet analysis · firewall logic · network telemetry

data

dashboards · backtesting · metrics pipelines

tools

APIs · automation · simulation · test harnesses